Mealy Machine Verilog Code Moore Machine Verilog Code. This page covers Mealy Machine Verilog Code and Moore Machine Verilog Code. Mealy Machine Verilog code. Following is the figure and verilog code of Mealy Machine.
This is a basic synchronous edge detection circuit.The input, siga, is sampled on each rising edge of the clock, clk. The sampled value is registered; that is, sigad1 is the value of siga delayed by one clock cycle.The output will go to a 1 when there is a rising edge on the input. The assignment to sigarisedge is responsible for this. It says that 'there was a rising edge on siga if the current value is 1 and the value on the previous clock cycle was 0'.Note that this will only work properly if the frequency of the input signal is lower than that of clock. If the input goes 0 - 1 - 0 all within a single clock period of the sampling clock, the edge may be missed.